The present invention relates to a semiconductor memory device, and more particularly, to a technology for increasing test efficiency by reducing the number of data pins needed for a test.
The present invention relates to a technology for reducing the number of data pins needed for a test of the semiconductor memory device; firstly, it will be described how data are transferred at a write time and a read time in a conventional semiconductor memory device.
FIG. 1 is a diagram illustrating a write path of a conventional semiconductor memory device.
In the drawing, the write path of data inputted to two data pads DQ0 and DQ1 is shown. Hereafter, a path of data inputted to the data pad DQ0 is referred to as a ‘first path’ and a path of data inputted to the data pad DQ1 is referred to as a ‘second path’ for purposes of clarity.
Data is sequentially inputted to the data pads DQ0 and DQ1 in series according to a Burst Length (BL). For instance, if the BL is 8, the data includes eight numbers that are sequentially inputted to the data pads DQ0 and DQ1 in series.
A first data input circuit 111 arrays data received through the data pad DQ0 in parallel and transfers the arrayed data to a first global bus GIO_D0_<0> to GIO_D0_<7>. A second data input circuit 121 arrays data received through the data pad DQ1 in parallel and transfers the arrayed data to a second global bus GIO_D1_<0> to GIO_D1_<7>.
Since the data includes eight numbers that are outputted from the first data input circuit 111 and the second data input circuit 121, each of the first global bus GIO_D0_<0> to GIO_D0_<7> and the second global bus GIO_D1_<0> to GIO_D1_<7> is configured with eight lines. As is well-known, the global buses GIO_D0_<0> to GIO_D0_<7> and GIO_D1_<0> to GIO_D1_<7> transfer data to all the banks (in FIG. 1, the data is illustrated as being transferred to a single bank).
Write driver units 112 and 122 are configured to transfer data, which is transferred to the global buses GIO_D0_<0> to GIO_D0_<7> and GIO_D1_<0> to GIO_D1_<7>, to local buses LIO_D0_<0> to LIO_D0_<7> and LIO_D1_<0> to LIO_D1_<7> in the bank. The first write driver unit 112 transfers data transferred to the first global bus GIO_D0_<0> to GIO_D0_<7> to the first local bus LIO_D0_<0> to LIO_D0_<7> in the bank. The second write driver unit 122 transfers data transferred to the second global bus GIO_D1_<0> to GIO_D1_<7> to the second local bus LIO_D1_<0> to LIO_D1_<7> in the bank.
Although local lines which connect the local buses LIO_D0_<0> to LIO_D0_<7> and LIO_D1_<0> to LIO_D1_<7> are normally configured as a pair of a main line and a sub line, i.e., LIO/LIOB, for transferring data, this is illustrated by only one line in the drawing.
FIG. 2 is a diagram showing a configuration of the first data input circuit 111. Since the second data input circuit 121 has the same configuration as the first data input circuit 111, the configuration of the second data input circuit 121 also can be understood with reference to FIG. 2.
The first input circuit 111 includes a buffer unit 210, an alignment unit 220 and a driver unit 230.
The buffer unit 210 buffers a data DATA_IN inputted in series from the first data pad DQ0. The alignment unit 220 aligns the buffered data in parallel and outputs the aligned data. In the example where the BL is 8, since eight numbers of data are sequentially inputted in series, the alignment unit 220 outputs eight numbers of data in parallel. The driver unit 230 is strobed by a strobe signal DINSTBP for determining a timing when a data is loaded on the first global bus GIO_D0_<0> to GIO_D0_<7>, and loads eight numbers of data on the first global bus GIO_D0_<0> to GIO_D0_<7> concurrently.
FIG. 3 is a diagram illustrating a read path of the conventional semiconductor memory device.
In the drawing, the read path of data outputted to two data pads DQ0 and DQ1 is shown. Also, in the same manner as the write path, a path of data outputted to the data pad DQ0 is referred to as a ‘first path’ and a path of data outputted to the data pad DQ1 is referred to as a ‘second path’ for purposes of clarity.
If a read command is applied to the memory device, data is outputted from the bank through the local buses LIO_D0_<0> to LIO_D0_<7> and LIO_D1_<0> to LIO_D1_<7>. The data transferred through the first local bus LIO_D0_<0> to LIO_D0_<7> is loaded on the first global bus GIO_D0_<0> to GIO_D0_<7> by a first sense amplifier unit 311 and the data transferred through the second local bus LIO_D1_<0> to LIO_D1_<7> is loaded on the second global bus GIO_D1_<0> to GIO_D1_<7> by a second sense amplifier unit 321. As shown in FIG. 3, each of the sense amplifier units 311 and 321 is configured with eight numbers of a sense amplifier IOSA. The sense amplifier IOSA is strobed by a strobe signal IOSTBP for determining a timing of when data is loaded on the global buses GIO_D0_<0> to GIO_D0_<7> and GIO_D1_<0> to GIO_D1_<7>. The sense amplifier IOSA also loads data from the local buses LIO_D0_<0> to LIO_D0_<7> and LIO_D1_<0> to LIO_D1_<7> on the global buses GIO_D0_<0> to GIO_D0_<7> and GIO_D1_<0> to GIO_D1_<7>.
A first data output circuit 312 aligns eight numbers of data transferred from the first global bus GIO_D0_<0> to GIO_D0_<7> in series and outputs the aligned data to the outside of the memory device through the first data pad DQ0. Also, the second data output circuit 322 aligns eight numbers of data transferred from the second global bus GIO_D1_<0> to GIO_D1_<7> in series and outputs the aligned data to the outside of the memory device through the second data pad DQ1.
FIG. 4 is a diagram illustrating a configuration of the first data output circuit 312. Since the second data output circuit 322 has the same configuration as the first data output circuit 312, a configuration of the second data output circuit 322 also can be understood with reference to FIG. 4.
The first data output circuit 312 includes a pipe latch 410 and an output driver 420. The pipe latch 410 aligns data transferred through the first global bus GIO_D0_<0> to GIO_D0_<7> in series and outputs the aligned data. In an example in which the BL is 8, since eight numbers of data should be sequentially outputted in series, the pipe latch 410 aligns eight numbers of data, which have been transferred in parallel, in series and outputs the aligned data. The output driver 420 outputs the data, which have been aligned in series, to the outside of the memory device through the first data pad DQ0.
Until now, manners in which data is read/written through the two data pads DQ0 and DQ1 have been described. However, in an x16 memory device, data is read/written through sixteen data pads DQ0 to DQ15; and, in an x32 memory device, data is read/written through thirty two data pads DQ0 to DQ31.
When the memory device is tested, the test is performed by assigning a channel to a data pad from test equipment. If an x16 memory device is tested, sixteen data channels are typically assigned to each memory device. The number of channels of the test equipment is, however, limited. Accordingly, if the number of channels needed for the test can be reduced, more memory devices can be tested with one test equipment. Therefore, if the number of data channels needed for the test, i.e., the number of data pads, can be reduced, the amount of time required to test the memory device may be reduced, and the costs associated with performing the test may also be reduced.